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Given TSMC’s 25% price increase for its 3-nanometer chip, the prices of the iPhone 15 series are likely to be far higher than anticipated. Report

Taiwanese contract chip manufacturer TSMC is reportedly increasing the price of wafers processed using its leading edge 3-nanometer process technology by 25% compared to 5-nanometer production node, Digitimes reported.

Whole one wafer processed on TSMC’s leading edge 3-nanometer manufacturing technology will cost over $20,000, the current 3-nanometer wafer costs around $16,000.

Given that Apple’s A17 bionic chip used in iPhone 15 Pro models will be made by TSMC’s 3-nanometer process node, the prices of Apple phones are likely to go up.

Apple’s A-series cellular system-on-a-chip (SoC), designed in house for the iPhone and iPad lineups based on ARM architecture, are exclusively manufactured by TSMC using its most advanced logic process technology.

The latest iPhone 14 Pro models use an A16 chip, which some have referred to as 4-nanometer, but seasoned industry observers characterise it as more of a die-shrunk 5-nanometer chip.

iPhone 13 model was powered by Apple’s A-series chipset, the A15 Bionic SoC, featuring an Apple-designed 64-bit 6-core CPU powered by two high-performance cores and four high energy-efficient cores. The chips were manufactured by TSMC using 5-nanomter manufacturing process.

As the world’s largest and most sophisticated contract chipmaker, TSMC produces the smallest, densest, and most power-efficient chips for fabless chipmakers like Advanced Micro Devices, Qualcomm, Nvidia, and Apple. The company’s dominant position in 7-manometer and 5-nanometer nodes gives its pricing power currently unmatched by rivals Samsung and Intel.

The Taiwanese chipmaker, which launched the 5-nanometer process in 2020, is scheduled to set to commercial production of the 3-nanometer process at its fab in Tainan city in Taiwan.

TSMC is following a different approach in developing its 3-nanometer technology by adopting the FinFet transistor structure, which it expects to deliver a high level of technology maturity, performance and cost for its customers.

Compared to its N5 manufacturing technology, the initial N3 fabrication process is projected to offer a 10-15 per cent performance improvement (at the same power and complexity), reduce power consumption by 25-30 per cent (at the same speed and transistor count), and increase logic density by around 1.6 times.

TSMC is also set to deploy its 3D chip stacking technology that it aims to boost its initial capacity 20 times by 2026.

With the industry’s traditional approach of cramming ever more transistors onto a single chip is starting is increasingly becoming challenging, the focus is now shifting to innovations around chip packaging.

3-nm chip to be produced in U.S

TSMC announced this week that it plans to produce its most advanced 3-nanometer chips in the U.S. as part of the company’s phase 2 plan at its plant in Phoenix, Arizona. The company’s new $12 billion semiconductor facility in U.S will begin by manufacturing 5-nanometer chips and the production of 3-nanometer chips would be in phase 2.

Apple CEO Tim Cook also said recently that his company is preparing to begin sourcing chips for its devices from a plant under construction in Arizona, marking a major step toward reducing the company’s reliance on Asian production.

Pointing out that 60 per cent of the world’s processor supply comes out of Taiwan, Cook said “Regardless of what you may feel and think, 60 per cent coming out of anywhere is probably not a strategic position,” he said.

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